CPU OVERVIEW AND CONTROL

CPU OVERVIEW

TABLE 1

Table 1 shows an abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them.

1.All instruction start by using the program counter (PC) to supply the instruction address to the instruction memory. (refer to red line)

2.After the instruction is fetched, the register operands used by an instruction are specified by fields of that instruction.(refer to blue line)

3.Once the register operands have been fetched, they can be operated on to compute a memory address (for a load or store), to compute an arithmetic result (for an integer arithmetic-logical instruction), or a compare (for a branch).

4.If the instruction is an arithmetic-logical instruction, the result from the ALU must be written to a register.
(refer to green line)

5.If the operation is a load or store, the ALU result is used as an address to either store a value from the registers or load a value from memory into the registers.(refer to orange line)

6.The result from the ALU or memory is written back into register file.

7.Branches require the use of the ALU output to determine the next instruction address, which comes either from the ALU (where the PC and branch offset are summed) or from an adder that increments the current PC by 4.

8. The thick lines interconnecting the functional units represent buses, which consists of multiple signals.

MULTIPLEXERS

TABLE 2

In practice, these data lines cannot simply be wired together; we must add a logic element that chooses from among the multiple sources and steers one of those sources to its destination. This selection is commonly done with a device called a multiplexor, although this device might better be called a data selector

DESIGN METHOD FOR CONTROL

--->Multi-level control (decoding)

--->Instruction opcode: main control unit (first level)

        – ALU control

             • Sub-control for arithmetic

       – MUX control

             • Which source registers and destination registers

             • ALU input source

             • Input source of destination register

             • Input source of PC

       – Result for first level

             • Seven 1-bit control lines

             • 2-bit ALUOP control signals

             • The above control signals can be set based solely on the opcode                     field of the instruction

                              # Exception: PCSrc (depends on the beq result)

CONTROL

TABLE 3

Table 3 shows the basic implementation of the MIPS subset, including the necessary multiplexors and control lines.

----> The top multiplexor (Mux) controls what value replaces the PC; the multiplexor is controlled by the gate that “ANDs” together the Zero output of the ALU and a control signal that indicates that the instruction is a branch.

----> The middle multiplexor, whose output returns to the register file, is used to steer the output of the ALU or the output of the data memory for writing into the register file.

----> Finally, the bottommost multiplexor is used to determine whether the second ALU input is from the registers or from the offset field of the instruction.

----> The added control lines are straightforward and determine the operation performed at the ALU, whether the data memory should be read or write, and whether the registers should perform a write operation.


----> The control lines are shown in blue colors.




BY AINI KHAIRANI BT AZMI